Implementation of DCC technique using differential amplifier based filter in 90nm CMOS technology
By: Landge, Lalita
.
Contributor(s): Jadhav, Usha.
Publisher: New Delhi Journals Pub 2019Edition: Vol.9(2), May-Aug.Description: 13-22p.Subject(s): EXTC EngineeringOnline resources: Click here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: Analog technique with feedback loop is applied to correct the duty cycle of any circuit without using more power. Pulse width modification is used to vary the duty cycle of clock signal. PMC cell is designed for expansion and contraction of pulse width. Differential amplifier based filter is used to detect the duty cycle of the particular clock signal. Differential amplifier and OpAmp are used to achieve adequate gain. The simulation is done in tanner EDA version_13 tool by using standard 90 nm technology. The schematic layout design of proposed DCC architecture is created in S-Edit. The system works at the frequency range of about 1 to 5 MHz.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
Articles Abstract Database
|
School of Engineering & Technology Archieval Section | Not for loan | 2020058 |
Analog technique with feedback loop is applied to correct the duty cycle of any circuit without using more power. Pulse width modification is used to vary the duty cycle of clock signal. PMC cell is designed for expansion and contraction of pulse width. Differential amplifier based filter is used to detect the duty cycle of the particular clock signal. Differential amplifier and OpAmp are used to achieve adequate gain. The simulation is done in tanner EDA version_13 tool by using standard 90 nm technology. The schematic layout design of proposed DCC architecture is created in S-Edit. The system works at the frequency range of about 1 to 5 MHz.
Click on an image to view it in the image viewer
There are no comments for this item.